Semiconductor Engineering· Qingpeng Wang·· 3 天前
自对准 CFET 架构仿真：SRAM 面积较 N3 缩小 52.7%
How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å
事实摘要
Semiverse Solutions 团队基于 SEMulator3D 数字孪生工艺建模，提出采用 SA-BPR、SA-CT、SA-TSV 三个自对准模块的 SA-CFET 架构，并据此设计出 6T SRAM 与 NOT、NAND、NOR 逻辑标准单元。
原文与核验
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正文 · 原文摘要
A process sequence for SRAM and logic that delivers higher performance through larger effective channel width and improved electrostatics at smaller nodes. The post How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å appeared first on Semiconductor Engineering .
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来源：Semiconductor Engineering · semiengineering.com