鲁尔大学、马普安全与隐私研究所与佐治亚理工研究硬件随机化缓存的实现开销与局限
Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)
鲁尔大学波鸿分校、马普安全与隐私研究所与佐治亚理工发表论文《Randomized Caches in Hardware: Challenges and Trade-offs》，将 CEASER-S、ScatterCache、SassCache 和 MIRAGE 四种随机化缓存设计集成为多核乱序 RISC-V SoC 的末级缓存（LLC）。
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Researchers at Ruhr University Bochum, the Max Planck Institute for Security and Privacy, and Georgia Tech published “Randomized Caches in Hardware: Challenges and Trade-offs.” Abstract Excerpt: “Randomized caches protect against side-channel attacks by obfuscating the mapping of memory addresses to cache locations. Existing proposals typically describe architectural behavior, leaving practical hardware implementation challenges largely unexplored.... » read more The post Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech) appeared first on Semiconductor Engineering .
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来源：Semiconductor Engineering · semiengineering.com
所属事件：三校研究：硬件随机化缓存的实现开销与局限